Case voor counter

In the previous Shift Register tutorial we saw that if we apply a serial data signal to the input of a Serial-in to Serial-out Shift Register, the same sequence of data will exit from the last flip flip in the register chain.

This serial movement of data through the resister occurs after a preset number of clock cycles thereby allowing the SISO register to act as a sort of time delay circuit to the original input data signal.

But what if we were to connect the output of this shift register back to its input so that the output from the last flip-flop, QD becomes the input of the first flip-flop, QA. We would then have a closed loop circuit that “recirculates” the same bit of DATA around a continuous loop for every state of its sequence, and this is the principal operation of a Ring Counter.

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